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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2004, zarlink semiconductor inc. all rights reserved. features ? current-controlled output current source ? output current per channel to 250 ma ? total output current to 300 ma ? rise time 1.0 ns, fall time 1.1 ns ? on-chip rf oscillator ? external resistor control of oscillator swing and frequency ? 200 to 500 mhz oscillator range ? 100 ma maximum oscillator swing ? single +5 v power supply (10%) ? low-power consumption ? common enable, disable input ? ttl/cmos control signals ? small ss016 package applications ?dvd r/rw ?cd r/rw october 2004 ordering information ZL40518LDG sso16 tape and reel 0 c to +70 c zl40518 3 channel laser diode driver data sheet figure 1 - functional block diagram iout vcc ch_2 ch_3 ch_r rf_freq rf_mag inr /enr in2 /en2 in3 /en3 rf rs gnd oscen pwr_up
zl40518 data sheet 2 zarlink semiconductor inc. figure 2 - pinout of 16 pin sso16 package (top view) description the zl40518 is a laser diode driver for high speed operatio n of a grounded laser diode. the driver consists of 3 controllable channels: a switchable, lo w noise, read channel and two swit chable write channels. write current pulses are enabled with the application of a low signal on the /en pins. a summed output of all channels is available at the iout pin. each chan nel can contribute up to 250 ma to the total output current of up to 300 ma. a total read channel gain of 100 and write channels 2 and 3 with a gain of 250 and 150 respectively are provided between each reference current input and output. laser mode hopping noise during read mode can be reduced by the use of an on-chip rf oscillator. the oscillator frequency and sw ing can be set by two external re sistors. the oscillato r is enabled by a high signal on the oscen pin and the entire device can be switched off by t he application of a low signal on the pwr_up pin. application notes read and write channel operation the read channel is activated by appl ying a 'high' signal to the pwr_up pin and applying a 'low' signal to /enr. in this mode, the fast write channels can be enabled by applyi ng a 'low signal to the respective pair of write enable pins (/en2) or (/en3). the output currents of the thr ee channels are summed together and output as a composite signal at iout. voltage control of the channel reference inputs (inr, in 2 and in3) can be achieved quite easily using an external resistor r ref in series with the reference channel input to convert a given reference potential v ref to an input current, i in : where r in is the input impedance of the respective reference channel. on-chip rf oscillator an on-chip rf oscillator is enabled if oscen = 'high' , and its output signal is added to the current output.the oscillator amplitude is set by an external resistor from rs to gnd. its frequency is set by an external resistor rf to gnd. the oscillator si gnal is summed with t he programmed write and read levels before amplification to the output. the oscillator signal has zero dc level and +i_pk to -i_pk signal swing. consequently, if the programmed dc level from the write and read channels is less than the pk level programmed for the oscillator, the combined inr in2 gnd rf in3 /enr /en2 /en3 vcc_in vcc iout gnd rs oscen vcc 1 3 12 13 6 8 4 2 10 5 7 9 11 14 15 16 pwr_up in ref ref in r r v i + = ,
zl40518 data sheet 3 zarlink semiconductor inc. signal will be clipped on the negative cycle of the signal. th is will increase the harmonic content of the output signal and reduce the pk to pk amplitude output. thermal considerations package thermal resistance is 40 c/w under the eia/jesd51-3 compliant pcb test board condition. users should ensure that the junction temp erature does not exceed 150 c. thermal resistance from junction to case and to ambient is very much dependent on how the ic is mounted onto the board, on the pcb layout and on any heat extraction arrangements. power cons umption and system ambient operati ng temperature limits should be noted and careful thermal gradient calculati ons undertaken to ensure that the junction temperature never exceeds 150 c. electrical and optical pulse response figure 3 - pulse response model figure 3 illustrates a simplified model of the typical z l40518 and the application. the zl40518 consist of an ideal switched current source and an equivalent model of the zl40518 output stage. the electrical model for the laser diode is a voltage source vd (v_on) in series with the on resistance rd all in parallel with the junction capacitance cd. this simplified model approximately re presents the laser diode elec trical load when operated beyond the laser threshold. to a firs t approximation, the optical output is pr oportional to the current flow in the resistor rd. the laser diode and the zl40518 are connec ted together by interconnect tracks with the return current passing through the supply decoupling bypass capacitor between ground and output vcc. the zl40518 will typically switch the programmed output current in 400 ps and can be approx imated to an ideal switch wi th a propagation delay of iout_on (1.2 ns). the electrical pulse response paramete rs, trise, tfall, overshoot and undershoot are determined by the combined electrical networ k as illustrated in figure 3. for example, the rise time and fall time for large cu rrent steps can be slew rate limited by the combined interconnect and fixed interconnect inductance. the fixe d inductance represents that associated with packaging and minimum interconnect distance . the interconnect induc tance is that associated with the additional tracking between laser diode and the zl40518 to acco mmodate application physical limitations. for example, if a pulse of 260 ma amplitude (40 ma to 300 ma) is to be switched in a time of 1 ns with the vd = 1.6 v, then the maximum volt drop across the interconnec t inductance is approximately 3.5 v (maximum vpin for 300 ma output) - 1.6 v (vdiode) = 1.9 v. consequently , l*di/dt < 1.9 v. hence , l < 1.9/ (0.26a/1ns) = 7.3 nh. en iout 500 17p 15 2p zl40518 model vd rd cd lint c_out lfix = 3nh lint=5nh , bw = 460mhz, rd=7, q=j20/(15+7) =0.9 lint=5nh, bw = 460mhz, rd=3, q=j20/(15+3) = 1.11 lint=7nh, bw = 411mhz, rd=7, q=j18/(15+7) = 0.8 lint=7nh, bw = 411mhz, rd=3, q=j18/(15+3) = 1.0 lint lfix = 3nh c_bypass k k vcc _a outa
zl40518 data sheet 4 zarlink semiconductor inc. small current step size rise and fall time will be determined by the bandw idth of the combined network. this is dominated by the interconnect inductance and the output capacitance. similarly, t he overshoot and undershoot will be determined by the q of the network. this is a fu nction of the source impedance from the zl40518, the interconnect inductance and the load impedance of the laser diode. figure 3 in cludes example simplified estimates of the q and bw of the combined laser diode, zl40518 and interconnect network for two different interconnect inductance values (5 nh & 7 nh) and two different diode on resistance (3 ohm & 7 ohm) . this simple analysis illustrates the change in bw and q of the network depending on these parameters. this in turn effects the rise time and fall time and the overshoot a nd undershoot performance ac hieved in the application. specified electrical performance with 15 mm interconnect and zarlink zle40518 evaluation board the specified performance in the table are results based on the electrical measurements and simulations across full process corners using the zarlink evaluation boar d using a 6.8 ohm resistive load to ground. the track interconnect between zl40518 and the 6.8 ohm resistor is 15 mm long and uses a 2 mm wide track on single sided fr4 board. the return path is via two 2 mm wide trac ks spaced 0.25 mm either side of the track between output and the 6.8 ohm resistor. the combined forward and return path forms a co planar transmission line with a characteristic impedance of approximately 120 ohms. the tight coupled return paths carrying the return current reduce the effective series inductance (leff) which can be approximated to:- l eff = 2 * lint * (1 - k) + 2 * lfix * (1 - k). the zle40518 board has two positions for the laser diode at two different distances. (15 and 30 mm). the measured value of l eff is 7 nh. the estimated value of l eff = 2 * 8 (1 - 0.5) = 8 nh. the actual pulse response achieved in an app lication is thus dependent on the application. application layer guide lines minimize interconnect inductance by:- a. using short interconnect distance b. use wide interconnect tracks c. keep the return path tightly coupled to the forward path
zl40518 data sheet 5 zarlink semiconductor inc. zle40518 interconnect figure 4 - zle40518 application board electrical interconnect application diagram figure 5 - evaluation board circuit inr in2 gnd rf in3 /enr /en2 /en3 vcc iout gnd rs pwr_up oscen vcc 1 3 12 13 4 8 4 2 10 5 7 9 11 14 15 16 digital inputs analog inputs vcc laser diode vcc_in
zl40518 data sheet 6 zarlink semiconductor inc. pin list pin no. pin name type function 1 inr analog read channel input current 2 in2 analog channel 2 input current 3 gnd supply ground 4 rf analog external resistor to groun d to set oscillator frequency 5 in3 analog channel 3 input current 6 /enr digital digital control of read channel (active low) 7 /en2 digital digital control of channel 2 (active low) 8 /en3 digital digital control of channel 3 (active low) 9 vcc supply +5 v supply 10 oscen digital enables rf oscillator (active high) 11 pwr_up digital device power up (active high) 12 rs analog external resistor to ground to set oscillator amplitude 13 gnd supply ground 14 iout analog output current for laser diode 15 vcc supply +5 v supply 16 vcc_in supply +5 v supply
zl40518 data sheet 7 zarlink semiconductor inc. absolute maximum ratings permanent damage may occur to any device stressed beyond the ?absolute maximum ratings?. operation at or beyond this stress rat ing is not implied for this or followi ng sections of this specif ication. device reliability can be affe cted by prolon ged exposure to absol ute maximum ratings. note 1: r thja 115c/w, t amb = 70 c note 2: r thja 115c/w, t amb = 25c operating range package thermal resistance note 1: measured with a multilayer test board (jedec standard). parameters symbol value unit supply voltage v cc -0.5 to +6.0 v input voltage at inr, in2, in3 v in1 -0.5 to +2.0 v input voltage at pwr_up, /enr, /en2, /en3, oscen v in2 -0.5 to v cc + 0.5 v output voltage v out -0.5 to v cc - 1 v power dissipation p max 0.7 1 to 1 2 w junction temperature t j 150 c storage temperature range t stg -65 to +125 c characteristic symbol units unit supply voltage range v cc 4.5 to 5.5 v input current i inr i in2 i in3 <2.5 <1.0 <1.7 ma external resistor to gnd to set oscillator frequency rf >3 k ? external resistor to gnd to set oscillator swing rs >2 k ? operating temperature range t amb 0 to +70 c parameters symbol value unit junction ambient r thja 115 1 k/w
zl40518 data sheet 8 zarlink semiconductor inc. electrical char acteristics - vcc = 5 v, t amb = 25 c, pwr_up = high, ch2 and ch3 disabled (/en2 = /en3 = high), read enabled (/enr = low), oscen = low, unless otherwise specified. * a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter parameters test conditions pin. symbol min. typ. max. unit type* power supply supply current, power down pwr_up = low, /en2 = /en3 = low 9, 15, 16 icc pd2 0.4 ma a supply current, read mode, oscillator disabled i inr =500 a, i in2 = 200 a, i in3 = 333 a 9, 15, 16 icc r1 86 ma a supply current, read mode, oscillator enabled i inr =500 a, i in2 = 200 a, i in3 = 333 a, oscen = high, rs = 7.5 k ? , rf = 7.5 k ? 9, 15, 16 icc r2 90 ma a supply current, write mode i inr =500 a, i in2 = 200 a, i in3 = 333 a, /en2 = /en3 = low 9, 15, 16 icc w 180 ma a supply current, input off i inr = i in2 = i in3 = 0 a 9, 15, 16 icc off 15 ma a digital inputs /enr, /en2, /en3 low voltage 6, 7, 8 vne lo 1.2 v a /enr, /en2, /en3 high voltage 6, 7, 8 vne hi 1.9 v a pwr_up low voltage 11 ven lo 0.5 v a pwr_up high voltage 11 ven hi 2.7 v a oscen low voltage 10 veo lo 0.5 v a oscen high voltage 10 veo hi 3.0 v a current at digital inputs /enr, /en2, /en3 low current /en = 0 v 6, 7, 8 ine lo -300 a c /enr, /en2, /en3 high current /en = 5 v 6, 7, 8 ine hi 800 a c pwr_up low current pwr_up = 0 v 11 ien lo -150 a c pwr_up high current pwr_up = 5 v 11 ien hi 100 a c oscen low current oscen = 0 v 10 ieo lo -100 a c oscen high current oscen = 5 v 10 ieo hi 800 a c
zl40518 data sheet 9 zarlink semiconductor inc. electrical ch aracteristics - vcc = 5 v, tamb = 25 c, pwr_up = high, unless otherwise specified. *a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note 1: linearity of the amplifier is calculated using a best fit method at three operating points of i out at 20 ma, 40 ma, and 60 ma. i out = (i in x gain) + i os parameters test conditions pin symbol min. typ. max. unit type* output iout total output current output is sourcing 14 i out 350 ma a output current per channel output is sourcing 14 i outr 250 ma a i out series resistance to ta l r out to v cc rail 14 r out 2 ? c best fit current gain inr channel r 1 14 gainr 90 100 130 ma/ ma a best fit current gain in2 channel 2 1 14 gain2 225 250 325 ma/ ma a best fit current gain in3 channel 3 1 14 gain3 135 150 195 ma/ ma a best fit current offset any channel 1 14 ios 2.6 ma a output current linearity any channel 1 14 ilin -3 +3 % a i in input impedance r in,inr is to gnd 1 r in,inr 500 ? c i in input impedance r in,in2 is to gnd 2 r in,in2 1250 ? c i in input impedance r in,in3 is to gnd 5 r in,in3 750 ? c en threshold temperature stabilised 6, 7, 8 vth 1.6 v c output off current 1 pwr_up = low 14 ioff 1 1 ma c output off current 2 /en2 = /en3 = high, i inr = 0, i in2 = 200 a, i in3 = 333 a 14 ioff 2 1 ma c output off current 3 /en2 = /en3 = low, i inr = i in2 = i in3 = 0 a 14 ioff 3 5 ma c i out supply sensitivity, write mode iout = 80 ma, 40 ma read + 40 ma write, vcc = 5 v +/- 10% 14 vse w 6 %/v c i out current output noise iout = 40 ma, oscen = low 14 ino o 3 na/rt- hz c
zl40518 data sheet 10 zarlink semiconductor inc. electrical characteristi cs: ac performance - vcc = 5 v, iout = 40 ma dc with 40 ma pulse, tamb = 25 c, unless otherwise specified. * a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note 1: load resistor at i out 6.8 ohms, measurement with 50 ohm oscilloscope and 39 ohm series resistor. parameters test conditions pin. symbol min. typ. max. unit type* output ac performance write rise time i out = 40 ma (read) + 40 ma (10 to 90%) 1 14 t rise 1.0 ns c write fall time i out = 40 ma (read) + 40 ma (10 to 90%) 1 14 t fall 1.1 ns c output current overshoot i out = 40 ma (read) + 40 ma 1 14 os 5 % c i out on propagation delay /en 50% high-low to i out at 50% of final value 14 t on 2.2 ns c i out off propagation delay /en 50% low-high to i out at 50% of final value 14 t off 2.0 ns c disable time pwr_up 50% high-low to iout at 50% of final value 14 t dis 20 ns c enable time pwr_up 50% low-high to iout at 50% of final value 14 t en 23 ns c amplifier bandwidth i out = 50 ma, all channels, -3 db value 14 bw lca 28 mhz c oscillator oscillator frequency rf = 7.5 k ? 14 f osc 288 322 352 mhz a osc. temperature coefficient rf = 7.5 k ? 14 tc osc +150 ppm/ c c disable time oscillator oscen 50% high-low to i out at 50% of final value 14 t diso 4 ns c enable time oscillator oscen 50% low-high to i out at 50% of final value 14 t eno 2 ns c
zl40518 data sheet 11 zarlink semiconductor inc. characteristic curves figure 6 - oscillator frequency vs rf (rs=7.5 k ? ) vcc = 5 v, temp = 25 c figure 7 - oscillator swing vs rs (rf=7.5 ? ) vcc = 5 v, temp = 25 c 200 300 400 500 600 700 800 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 11.00 12.00 rf (kohm) frequency (mhz) 0 20 40 60 80 100 120 2345678910 rs (kohms) amplitude (mapk-pk)
zl40518 data sheet 12 zarlink semiconductor inc. figure 8 - oscillator frequency dependency of swing vcc = 5 v, temp = 25 c figure 9 - transfer char acteristic of channel 2 (gain = 278, load resistor at iout = 6.8 ? ) 0 10 20 30 40 50 60 200 250 300 350 400 450 500 frequency (mhz) amplitude (mapk-pk ) 0 100 200 300 400 500 0 200 400 600 800 1000 1200 1400 1600 1800 2000 input current (ua) iout (ma)
zl40518 data sheet 13 zarlink semiconductor inc. figure 10 - voltage compliance r (iout to vcc) = 2.0 ? figure 11 - step response, read channel: 50 ma, channel 2: 50mapp 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0123456 vout (v) iout (a)
zl40518 data sheet 14 zarlink semiconductor inc. figure 12 - step response, read channel: 50 ma, channel 2: 250mapp timing waveforms figure 13 - output waveform showing addition of read and write levels t pwr_up /enr /en2 /en3 en t on t on t off t off t dis t r t r t r t r

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